Delay locked loops (DLLs) are often used in integrated circuits (ICs) to generate an internal clock signal. In a typical DLL, the internal clock signal is generated by applying an amount of delay to a system clock or an external clock signal. The DLL tracks the external and internal clock signals with a detect operation and adjusts the amount of delay with a shifting operation to keep the internal and external clock signals synchronized.
In some integrated circuit devices, such as dynamic random access memory (DRAM) devices, the internal clock signal generated by the DLL is normally used as a timing signal for certain operations of the memory device. For example, in some memory devices, the internal clock signal can be used as a clock signal to provide timing for data transfer to and from the memory device.
One type of DLL includes a variable delay line circuit having both a fine delay line and a course delay line coupled in serial. In operation, timing delay of the fine and course delay lines are adjusted and reset as needed for clock signal synchronization. These adjust and reset operations can provide undesired results in the timing of the internal clock signal.
For reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for methods and devices to synchronize signals in an integrated circuit device such as a memory device.